In order to make this tutorial interesting, I opted to design a 4V to 24V boost converter with calculations. I simplified most of the discussions for easier understanding especially to beginners. Should you have any questions, kindly leave a comment in the comment section.
1. Design Requirements
We will start with the requirements. The design will proceed based on below specifications.
2. Topology
Since the efficiency requirement is very high, we will select a synchronous boost converter. A synchronous boost converter uses an electronic switch such as MOSFET, IGBT or BJT for the boost diode section. Boost diode has significant forward voltage drop that will result to high power loss. On the other hand, electronic switches such as mentioned above will have very low power loss.
3. Power Loss Budget
It is a good idea to distribute power loss to the devices. This is to optimize the design in terms of component cost and meeting the requirements. With the power loss budget, the design engineer will be guided to what electrical ratings of the devices to use. Without the power loss budget in the early design will also work but the process may take multiple trial an error.
The 93% efficiency means a total power loss of
Power Loss Budget = [ ( 1 / 0.93 ) – 1 ] x Pout = [ ( 1 / 0.93 ) – 1 ] x 120 W = 9 W
From the total power loss budget, let us assume below distribution.
If we can attain losses lower than this, that would be great. However, there could be cost impact.
4. Controller Selection
The controller selected for this design is LM51231-Q1. It is an automotive qualified synchronous boost controller from Texas Instruments. Its minimum input voltage is 3.8V while can support up to 57V output voltage. Its operating frequency range is 100 kHz to 2.2 MHz, and its operating temperature is -40’C to +125’C. Thus, this is a god fit for the design.
5. Determine the Device Currents
To size up the devices, the currents of the MOSFETs and the inductor must be known. The voltage of the MOSFETs must also be defined. But this is simple to determine as compared to the currents. As a rule of thumb, select MOSFET with voltage rating of at least 2.5 times the maximum output voltage. In our example here, the MOSFET voltage must not less than 2.5 x 24V = 60V.
Procedure to Determine the Device Currents
5.1. Compute the Duty Cycle
The duty cycle of a boost converter (conventional or synchronous type) is can be expressed as detailed and ideal form. The detailed form includes the voltage drop of the power switches or diode. On the other hand, the ideal duty cycle does not include the voltage drop of the power devices.
Where:
Vin is the input voltage, Vout is the output voltage, Vd is the voltage drop of the boost diode (for a synchronous boost converter, this is the drop of the switch Q2 in the sample circuit above) and Vsw is the voltage drop of the switch Q1 in the sample circuit above
In this sample design, let us use the ideal duty cycle form. The computed duty cycle is
The next step is to compute the minimum inductance needed. The minimum inductance must be sized accordingly to set the operation in the continuous conduction mode (CCM). CCM is preferred since the peak of the currents are low, that will result to a higher efficiency compared to boundary mode and discontinuous conduction mode (DCM).
The minimum inductance equation is given below.
L minimum = Duty x Vin / ( Iripple x Fsw )
Where:
Duty is the duty cycle (ideal or detailed, but in this sample design, let it be ideal), Vin is the input voltage, Fsw is the switching frequency and Iripple is the target ripple current of the inductor. Iripple can be assumed to be 40%-60% of the input current.
The input current is can be computed using below equation
I input = Vout x Iout / Vin = 24V x 5A / 4V = 30 A
In this sample design, we will assume an inductor ripple current of 50% of the input current. Thus, the minimum inductance we need is
L minimum = Duty x Vin / ( Iripple x Fsw ) = 83.33% x 4V / ( 50% x 30A x 500 kHz) = 0.44 uH
5.3. Select Actual Inductance
The computed inductance in step 5.2 is based on the ripple assumption. The design engineer can choose any standard inductance value higher than the computed value. In this design sample, we will select 1uH inductance value.
5.4. Actual Inductor Ripple Current
Since the actual inductance value is selected, the actual ripple current can be computed. In this design sample, it is
di = Duty x Vin / (Lselected x Fsw ) = 83.33% x 4V / ( 1 uH x 500 kHz ) = 6.66 A
5.5. Peak Current
Next step is to determine the peak current. This peak current is common for the inductor, switch and diode (L1, Q1 and Q2 in the sample circuit above).
Using the values derived for Ipeak and di above, the inductor RMS current is
Irms Inductor = Ipeak – 0.423 x di = 33.27 A – 0.423 x 6.66 A = 30.45 A
Select an inductor with a saturation current higher than the value of Ipeak, which is 33.27A in this design sample and with an RMS rating of higher than 30.45A. Setting the maximum stress to 80% is a good practice.
5.7. Switch Q1 Current Calculation
The equation of the RMS current through Q1 is
Irms Q1 = sqrt ( Duty / 3 ) x di + sqrt ( Duty ) x ( Ipeak – di )
Using the values we derived above, the RMS current of Q1 is
Irms Q1 = sqrt ( 83.33% / 3 ) x 6.66 A + sqrt ( 83.33% ) x ( 33.27 A – 6.66 A ) = 27.8 A
Thus, select a MOSFET for Q1 with a peak current higher than 33.27A and with an RMS current higher than 27.8A.
5.8. Switch Q2 Current Calculation
The equation of the RMS current of switch Q2 (this is valid also to boost diode if non-synchronous boost is used) is given below
Irms Q2 = di x sqrt [ (1 – Duty) / 3 ] + ( Ipeak – di ) x sqrt ( 1 – Duty )
Using the values we derived above, the RMS current of switch Q2 is
Irms Q2 = 6.66 A x sqrt [ (1 – 83.33%) / 3 ] + ( 33.27 A – 6.66 A ) x sqrt ( 1 – 83.33% ) = 12.44 A
Select a MOSFET for Q2 that can handle a peak current of 33.27A and an RMS current of 12.44A.
6. Select Actual Devices
6.1. MOSFET Q1 and Q2 Selection
From the power budget in the above section, the total MOSFET losses is not to exceed 7W. For a MOSFET, the power losses are composed of conduction and switching losses. Conduction loss is due to the drain to source on state resistance of the MOSFET. Switching loss is due to the parameters that are dependent to switching action (COSS, total gate charge and rise and fall times). For more information about conduction and switching losses, read
In this design example, I have tried some MOSFETs. Some with very low RDSon (drain to source on-state resistance) but with high parasitic parameters, some has high RDSon but low parasitic parameters. Nothing meets the budgeted power loss (a total of 7W for all the MOSFETs). Until I decided to put two MOSFETs in parallel for the location of Q1 and Q2. I used a MOSFET with not so low RDSon but the parasitic parameters are not so high to meet the power loss budget. I did not show any more here my iterations but I have a tool that can compare MOSFET power losses. You can download it
The summary of the MOSFET power losses is given in the table below.
There are two MOSFETs in location Q1 and Q2. So, the total power loss of the MOSFETs is
2 x 2.248 W + 2 x 0.755 W = 6 W
The target total power loss of the MOSFETs must not more than 7 W, based on the power loss budget we define earlier. Therefore, we meet our goal for the MOSFETs.
In this design sample, I choose same MOSFET for the Q1 and Q2 locations. This is not a standard practice. You can choose different MOSFETs for each location. In some cases, it is economical to choose different MOSFETs. As you observed from the power loss table above, the MOSFET in the Q2 location has lower power loss. With this, you can use a MOSFET with a little higher Rdson and parasitic parameters since that kind of MOSFET is cheaper. However, in our design sample, I have no option because the efficiency requirement is too high and prevails over a possible cost saving in using a cheaper but low performance MOSFET.
6.2. MOSFET Electrical Stresses
The MOSFET maximum voltage rating is 60V. This enough for a 24V boost output. In case in actual test the voltage across the drain to source is going to exceed 60V, consider adding snubber. Read Snubber Circuit Design Analysis for guidance.
If adding a snubber will add complications, redo the process of MOSFET selection and select a device with higher voltage rating.
The current rating of the selected MOSFET is very high compared to the calculated value. Thus, it has no issue.
Let us check the power stress of the MOSFETs. First, we will consider not using an external heatsink. If the power stress is still below 80%, this is great because external heatsink means more cost and need bigger space. To do so, use below equation.
MOSFET Power Capability, no heatsink = ( Tjmax – Ta_max ) / Rthja
Where:
Tjmax – is the maximum junction temperature of the MOSFET specified in the datasheet.
For the selected MOSFET, it is 175’C.
Ta_max – is the maximum ambient temperature of application (design requirement). In this sample design, it is 50’C.
Rthja – is the thermal resistance from junction to ambient. For the selected MOSFET, it is 68’C/W.
Substituting the values,
MOSFET Power Capability, no heatsink = ( 175 – 50 ) / 68 = 1.84 W
The total power loss of each of the MOSFET in Q1 location is 2.248 W. The corresponding power stress without external heatsink is 122% (2.248/1.84).
The power stress is more than 100%. This is not going to work. Let us examine the thermal resistance specified in the datasheet. There is a comment in the datasheet which says the 68’C/W is when the MOSFET is mounted in a 1” square PCB (FR4 material).
If we can lower the thermal resistance of the MOSFET by 20’C/W, the stress level will decrease to around 86%. This is already workable.
There is no more information about the mounting pad aside from the 1” square, but in most cases, this is just a 1 oz thick copper and two layers (top and bottom). We can increase the mounting pad area by increasing the thickness, and consider a 4-layer PCB with via stitching, the thermal resistance will go down and the 20’C/W reduction is very possible. I don’t want to use an external heatsink because it is not easy for the MOSFET I selected.
The MOSFETs in the location Q2 has no problem using the minimum pad requirements specified in the datasheet.
6.3. Actual Inductor Selection
The inductor selected is IHLP8787MZER1R0M51 from Vishay. It has 1uH inductance that is higher than the value we computed. This is fine, the more the boost converter to operate in the continuous conduction mode (CCM). CCM is the preferred mode because it can help us in achieving high efficiency. The typical DC resistance is 0.00082 ohms.
With the computed inductor RMS current, this results to a power loss of 0.764W.
7. Over Current Setting
Over current setting is very important. It will protect the converter for over current and short circuit scenarios. The over current setting requires sense resistor to detect the current in the inductor. This resistor will result to a power loss and will impact the efficiency.
For the controller I selected in this sample design, the sense resistor is can be determined using below equation.
Ipeak_CL = 0.06 / Rsense
Where:
Ipeak_CL – is the peak inductor current during current limit Rs – is the sense resistor value
The current limit value is a current that above the maximum current or full load current specification. This sample design specified a 120% current limit. This is equal to 6A.
For 6A over current limit (Iout_CL), the corresponding inductor peak current (Ipeak_CL) is determined using below equation
I peak_CL = [ Iout_CL / ( 1 – Duty ) ] + ( di /2 ) = [ 6 A / ( 1 – 83.33% ) ] + ( 6.66 A / 2 ) = 39.26 A
Expressing Rs from the Ipeak_CL equation given above, will give the size of the sense resistor.
The power loss due to the sense resistor (Rs) is determined using below equation
Ploss sense resistor = Irms_inductor x Irms_inductor x Rsense
For full load condition, the power loss of the sense resistor is
Ploss sense resistor full load = 30.45 x 30.45 x 0.0015 = 1.39 W
This is the power loss to consider in calculating the efficiency. We are not going to consider the power loss at the current limit because efficiency is only expected at the normal operation. Operating at the current limit is not considered normal.
To size up the wattage of the sense resistor, the power loss at the over current setting must be considered. Below is the computation.
Ploss Rsense over current = Irms_inductor (over current) x Irms_inductor (over current) x Rsense
The current in the inductor during over current of 6A is 36.44 A. This result to a power dissipation on the sense resistor of
Ploss Rsense over current = 36.44 A x 36.44 A x 0.0015 ohm = 1.99 W
So, the sense resistor must be 1.5 milliohm and at least 2.5 W of power rating. This gives around 80% power stress on the sense resistor.
In this sample design, I am going to select MSMA2512R0015FGM of Eaton Electronics. It is 1.5 milliohm and a power rating of 3W in a 2512 SMD package.
8. Efficiency Calculation
The total power loss is
Ploss total = Ploss MOSFET total + Ploss inductor + Ploss sense resistor = 6 W + 0.764 W + 1.39 W = 8.154 W
Efficiency = Pout / (Pout + Ploss) = 120 W / (120 W + 8.154 W) = 93.64%
We meet our target efficiency. However, in actual testing, there could be some power losses due to traces and other factors that we could not able to calculate. Good thing that we still have margin 0.6% margin.
9. Complete Circuit and PCB Layout
This is the complete schematics diagram. Some values are just copied from the datasheet application example.
Below is the complete PCB layout using above circuit.
If you want to try the design, download it
here. I can give the BOM also. Just leave a comment about your experience you we can continuously improve this design to help everybody.
10. Recommended PCB Layout
The recommended PCB layout from Texas Instruments is shown below. The actual PCB layout is copied from this recommendation.
Based on the MOSFET datasheet, the thermal resistance from junction to ambient is 68 ‘C/W. This is based on a 1 square inch PCB (FR4 material).
In order to meet this, I used a 4-layer PCB and the MOSFET mounting pad is utilizing these 4 layers. The total area is significantly bigger. Thus, I can ensure that the MOSFETs can withstand the temperature even without heatsink.
